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Instruction scheduling
Results: 85

#	Item
11	Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers Stephen Hines, David Whalley, Gary Tyson Computer Science Department Florida State University Tallahassee, FL Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2006-08-24 08:01:51 Compiler optimizations Assembly languages Instruction scheduling Reduced instruction set computing Instruction set Branch predication Register renaming Very long instruction word Addressing mode Computer architecture Computing Computer engineering
12	Swing Modulo Scheduling for GCC Mostafa Hagog IBM Research Lab in Haifa Ayal Zaks IBM Research Lab in Haifa Add to Reading List Source URL: gcc.cybermirror.org Language: English - Date: 2004-08-29 18:00:00 Programming language implementation Instruction scheduling Software pipelining Scheduling GNU Compiler Collection Parallel computing Static single assignment form Assembly language Software Compiler optimizations Computing
13	Eliminating Cache-Based Timing Attacks with Instruction-Based Scheduling Deian Stefan1 , Pablo Buiras2 , Edward Z. Yang1 , Amit Levy1 , David Terei1 , Alejandro Russo2 , and David Mazières1 1 Add to Reading List Source URL: www.scs.stanford.edu - Date: 2014-12-02 06:10:54
14	POOL ENVIRONMENTS, INC. INSTRUCTION MANUAL / TROUBLE SHOOTING GUIDE MARC VALENTINI –Client Services Manager MOBILECYNTHIA HALLIBURTON – SERVICE COORDINATOR & SCHEDULING Add to Reading List Source URL: poolenvironments.com - Date: 2015-01-22 12:19:55
15	POOL ENVIRONMENTS, INC. INSTRUCTION MANUAL / TROUBLE SHOOTING GUIDE MARC VALENTINI –Client Services Manager MOBILECYNTHIA HALLIBURTON – SERVICE COORDINATOR & SCHEDULING Add to Reading List Source URL: poolenvironments.com Language: English - Date: 2015-01-22 12:19:57
16	Formal Verification of Translation Validators A Case Study on Instruction Scheduling Optimizations Jean-Baptiste Tristan Xavier Leroy Add to Reading List Source URL: cristal.inria.fr Language: English - Date: 2007-11-09 01:03:49
17	Exploring Circuit Timing-aware Languages and Compilation Giang Hoang Robert Bruce Findler Russ Joseph Add to Reading List Source URL: users.eecs.northwestern.edu Language: English - Date: 2011-03-04 16:19:11 Software Compiler construction Compiler optimization Instruction scheduling Dynamic random-access memory Compiler Program optimization Formal methods Programming language implementation Software engineering Computing
18	Eliminating Cache-Based Timing Attacks with Instruction-Based Scheduling Deian Stefan1 , Pablo Buiras2 , Edward Yang1 , Amit Levy1 , David Terei1 , Alejandro Russo2 , and David Mazières 1 Add to Reading List Source URL: www.amitlevy.com Language: English - Date: 2013-09-13 15:42:52 Cache Computer memory Computer architecture Scheduling Thread Timing attack Computing Central processing unit CPU cache
19	A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors Josep M. Codina, Jesús Sánchez and Antonio González Department of Computer Architecture Universitat Politècnica de Catalunya Barc Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:01 Parallel computing Concurrent computing Central processing unit Instruction scheduling Very long instruction word Register allocation Computer cluster Processor register Thread Computing Computer architecture Compiler optimizations
20	MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARTIFICIAL INTELLIGENCE LABORATORY A.I. Memo NoApril 1993 Add to Reading List Source URL: repository.readscheme.org Language: English - Date: 2010-10-22 08:05:37 Computer architecture Compiler optimizations Microprocessors Very long instruction word Central processing unit Scheduling Software pipelining Stream processing Multi-core processor Computing Concurrent computing Parallel computing

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